1. Technical Field
This disclosure relates to computer systems, and more particularly, memory subsystems.
2. Description of the Related Art
Computer systems typically include a main memory implemented on one or more integrated circuits (ICs) separate from a processor. The main memory in many systems is implemented using dynamic random access memory. The processor may access the memory for data and instructions during operations. Many modern processors include one or more processor cores, each of which may include its own execution units, registers, and so on.
To improve performance a processor may implement one or more levels of cache memory in each of its one or more cores. A cache memory may store frequently accessed data and/or instructions in an on-chip memory closer to execution units of the processor. Caches may be implemented in multiple levels, e.g., Level One (L1), L2, L3, etc. An L1 cache may be the closest cache to an execution unit in a processor, and L2 may be the next level, and so forth. In some cases, such as with L1 caches, separate caches may be provided for instructions and data.
Cache subsystems are hardware based systems. That is, a cache subsystem may be transparent to an operating system (OS) or other software executing on a processor core. In addition to storing data, a cache may also store extra information, such as a tag, to identify cache lines. A tag may include a certain number of bits. Generally speaking, for a given cache line size, the larger the cache (and thus, the greater number of cache lines), the greater number of bits used in the tag.